A task will be assigned on 15th May at 12:00 PM UTC+3 and you will have 24 hours to complete it.
Test your skills by solving the task using one of the following Hardware Description Languages: VHDL, Verilog or System Verilog.
The completed project must include both design and simulation (verification).

Task example: Create and verify a synthesizable Advanced Peripheral Bus (APB) and an SPI Master then connect them together under a Top Module.